1. Field of the Invention
The invention relates generally to the testing of semiconductor circuits and more particularly, to die carriers used to make electrical contact with the pads of a bare semiconductor circuit die during functional and burn-in testing.
2. Description of the Related Art
A major challenge in the production of multichip modules is the identification of defective integrated circuit chips. The yield rate of multichip modules can be significantly increased through the use of fully tested and burned-in die. The testing of die prior to packaging or assembly into multichip modules reduces the amount of rework which in turn decreases manufacturing costs.
Functional tests determine whether a semiconductor circuit operates in accordance with prescribed specifications. Burn-in tests identify latent or inherent manufacturing defects caused by factors like contamination or process variations during manufacture. Such defects can cause early failure. Burn-in tests subject the die to electrical stress at high power supply voltages with increased temperatures so as to accelerate such early failure to the point of detection.
One problem with the testing of bare die is that as circuit dimensions have become smaller, so have the pads on the die surfaces. Moreover, these smaller pads often are packed more closely together. As a result, it sometimes can be impractical to use devices such as probe cards to make electrical contact with die pads for testing purposes. Another problem with probe cards has been their relatively poor performance in testing high frequency signals.
Some of the shortcomings of probe cards have been overcome through the use of temporary die carriers. For example, gold can be applied to the contact pads of a die, and the die can be placed in a temporary carrier in which it is held in electrical contact with gold pads on the carrier through the application of pressure to the pad-to-pad interface. The use of gold, however, can be too expensive for many semiconductor processes. Another approach is to wire bond the die pads to an intermediate test package. Although the die can be removed from the package after testing by removal of the wire bonds, this can result in damage to the circuit. Consequently, some manufacturers include both the die and its intermediate test package in the final IC package in order to reduce the possibility of such damage.
Still another approach is disclosed in U.S. Pat. No. 5,123,850 issued to Elder et. al. which teaches the use of an interconnect circuit formed in a resilient membrane to make temporary electrical contact with pads disposed on a die. The interconnect circuit is formed from alternating layers of polyimide dielectric and metal signal lines. Electrical contact bumps protrude from a top surface of the membrane and make electrical contact with individual signal lines. A semiconductor die is placed on the membrane and is aligned by visible means to ensure that the contact bumps are disposed opposite pads on the die. An insert plate is placed against a bottom surface of the membrane opposite the die. The interconnect circuit is wire bonded to a pin grid array (PGA) which can be plugged into a test socket base to communicate test signals to and from the carrier. A heat sink is clipped to the PGA, and the die is pressed between the heat sink and the membrane. The force exerted against the die is expected to cause the contact bumps to make electrical contact with the die pads.
While earlier carriers such as the one described above contain good design concepts there have been shortcomings with their use. For example, the gold coated bumps on the contact pads often do not make adequate contact with the die pads because of the build-up of an oxide layer on the die pads. In addition, the use of visual means to align the die with the flexible membrane can be somewhat clumsy and time consuming or may require elaborate vision and robotic systems. The use of wire bonding and the use of a PGA can be expensive. The wire bonding of the interconnect circuit to the PGA can make it difficult to interchange one interconnect circuit configured to test one type of die with another interconnect circuit configured to test another type of die. Furthermore, using the heat sink cavity to hold the die aligned to the membrane can be impractical and expensive.
Thus, there has been a need for an improved carrier for testing bare semiconductor circuit die. There has been a particular need for a carrier in which a flexible interconnect circuit can be easily aligned with the pads of a die. There also has been a need for an improved contact pad structure that can penetrate an oxide layer on the die pads. Furthermore, there has been a need for such a carrier in which test signals can be communicated to and from the carrier without the need to make wire bond connections or to use relatively expensive intermediate circuits such as PGAs to conduct signals to and from the carrier. In addition, there has been a need for a carrier in which one interconnect circuit can be readily interchanged with another interconnect circuit. The present invention meets these needs.